vishay siliconix dg3157 document number: 72648 s09-0294-rev. d, 23-feb-09 www.vishay.com 1 high-speed, low r on , spdt analog switch (2:1 multiplexer/de multiplexer bus switch) features ? halogen-free according to iec 61249-2-21 ? direct cross to industry standard sn74lvc1g3157, nc7sb3157, nlasb3175, pl5a31 57, and stg3157 ? sc-70 6-lead package ? 1.65 v to 5.5 v v cc operation ?5 connection between ports ? minimal propagation delay ? break-before-make switching ? zero bounce in flow-through mode description the dg3157 is a high-speed single-pole double-throw, low power, ttl-compatible bus switch. using sub-micro cmos technology, the dg3157 achieves low on-resistance and negligible propagation delay. the dg3157 can handle both analog and digital signals and permits signals with amplitudes of up to v cc to be transmitted in either direction. when the select pin is low, b 0 is connected to the output a pin. when the select pin is high, b 1 is connected to the output a pin. the path that is open will have a high- impedance state with respect to the output. make-before- break is guaranteed. an eptiaxial layer prevents latch-up. functional block diagram and pin configuration s a 1 2 3 6 top view b 1 gnd b 0 4 sc-70 6-pin 5 v+ device marking: g1 truth table logic input (s) function 0 b 0 connected to a 1 b 1 connected to a ordering information temp. range package part number - 40 c to 85 c sc-70-6 dg3157dl-t1-e3 DG3157DL-T1-GE3 (halogen-free)
www.vishay.com 2 document number: 72648 s09-0294-rev. d, 23-feb-09 vishay siliconix dg3157 notes: a. signals on a, or b or s exceeding v+ will be clamped by internal diodes. limit forwar d diode current to maximum current ratin gs. b. all leads welded or soldered to pc board. c. derate 3.1 mw/c above 70 c. absolute maximum ratings parameter limit unit reference v+ to gnd - 0.3 to + 6 v s, a, b a - 0.3 to (v+ + 0.3) continuous current (any terminal) 50 ma peak current (pulsed at 1 ms, 10 % duty cycle) 200 storage temperature d suffix - 65 to 150 c power dissipation (packages) b 6-pin sc-70 c 250 mw specifications parameter symbol test conditions unless otherwise specified v+ = 3.0 v, v s = 0.25 v to 0.7 v+ e temp. a limits - 40 c to 85 c unit min. b typ. c max. b dc characteristics high level input voltage v sh v+ = 1.65 to 1.95 v full 0.75 v+ v v+ = 2.3 to 5.5 v full 0.7 v+ low level input voltage v sl v+ = 1.65 to 1.95 v full 0.25 v+ v+ = 2.3 to 5.5 v full 0.3 v+ on resistance r on v+ = 4.5 v v bn = 0 v, i a = 30 ma full 6 7 v bn = 2.3 v, i a = - 30 ma full 6 12 v bn = 4.5 v, i a = - 30 ma full 9 15 v+ = 3.0 v v bn = 0 v, i a = 24 ma full 8 9 v bn = 3.0 v, i a = - 24 ma full 12 20 v+ = 2.3 v v bn = 0 v, i a = 8 ma full 9 12 v bn = 2.3 v, i a = - 8 ma full 13 30 v+ = 1.65 v v bn = 0 v, i a = 4 ma full 12 20 v bn = 1.8 v, i a = - 4 ma full 18 50 on resistance flatness r flat 0 < v bn < v+ v+ = 4.5 v, i a = - 30 ma room 6 v+ = 3.0 v, i a = - 24 ma room 12 v+ = 2.3 v, i a = - 8 ma room 22 v+ = 1.65 v, i a = - 4 ma room 90 on resistance matching between channels r on v+ = 4.5 v, v bn = 3.15 v, i a = - 30 ma room 0.32 v+ = 3.0 v, v bn = 2.1 v, i a = - 24 ma room 0.31 v+ = 2.3 v, v bn = 1.6 v, i a = - 8 ma room 0.30 v+ = 1.65 v, v bn = 1.15 v, i a = - 4 ma room 0.29 input leakage current i s v+ = 5.5 v, v a = 5.5 v room full - 0.1 - 1.0 0.1 - 1.0 a off stage switch leakage i bn(off) v+ = 5.5 v, v a /v b = 0 v/5.5 v room full - 0.1 - 1.0 0.1 - 1.0 on state switch leakage i bn(on) v+ = 5.5 v, v a /v b = 0 v/5.5 v room full - 0.1 - 1.0 0.1 - 1.0
document number: 72648 s09-0294-rev. d, 23-feb-09 www.vishay.com 3 vishay siliconix dg3157 notes: a. room = 25 c, full = as determined by the operating suffix. b. the algebraic convention whereby the most negative value is a minimum and the most pos itive a maximum, is used in this data sheet. c. typical values are for design aid only, not guaranteed nor subject to production testing. d. guarantee by design, nor subjected to production test. e. v in = input voltage to perform proper function. f. guaranteed by design and not production tested. the bus switch propagation delay is a function of the rc time constant contr ibuted by the on-resistance and the specified load capacit ance with an ideal voltage source (zer o output impedance) driving the switch. stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indi cated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended per iods may affect device reliability. specifications parameter symbol test conditions unless otherwise specified v+ = 3.0 v, v s = 0.25 v to 0.7 v+ e temp. a limits - 40 c to 85 c unit min. b typ. c max. b power supply power supply range v+ full 1.65 5.5 v quiescent supply current i+ v+ = 5.5 v, v a = v b = v+ or gnd room full 1 10 a ac electrical characteristice prop delay time f t phl /t plh v a = 0 v v+ = 1.65 to 1.95 v full ns v+ = 2.3 to 2.7 v full 1.2 v+ = 3.0 to 3.6 v full 0.8 v+ = 4.5 to 5.5 v full 0.3 output enable time f t pzl /t pzh v load = 2 x v+ for t pzl v load = 0 v for t pzh v+ = 1.65 to 1.95 v room full 10.2 10.4 v+ = 2.3 to 2.7 v room full 5.9 6.2 v+ = 3.0 to 3.6 v room full 4.1 4.5 v+ = 4.5 to 5.5 v room full 2.6 2.9 output disable time f t plz /t phz v load = 2 x v+ for t plz v load = 0 v for t phz v+ = 1.65 to 1.95 v room full 10.2 10.4 v+ = 2.3 to 2.7 v room full 5.9 6.2 v+ = 3.0 to 3.6 v room full 4.1 4.5 v+ = 4.5 to 5.5 v room full 2.6 2.9 break-before-make time d t bbm v+ = 1.65 to 1.95 v full 0.5 v+ = 2.3 to 2.7 v full 0.5 v+ = 3.0 to 3.65 full 0.5 v+ = 4.5 to 5.5 v full 0.5 charge injection d q c l = 0.1 nf, v gen = 0 v r gen = 0 v+ = 5 v room 7 pc v+ = 3.3 v room 3 analog switch characteristics off isolation d oirr r l = 50 , f = 10 mhz room - 57.6 db crosstalk d x ta l k room - 58.7 - 3 db bandwidth d bw r l = 50 room > 250 mhz capacitance control pin capacitance d c in v+ = 0 v room 4.9 pf b port off capacitance d c io-b v+ = 5 v room < 6.5 a port capacitance when switch enable d c io-a(on) room < 18.5
www.vishay.com 4 document number: 72648 s09-0294-rev. d, 23-feb-09 vishay siliconix dg3157 logic diagram positive logic typical characteristics 25 c, unless otherwise noted figure 1. a b 1 b 0 s r on vs. v a vs. v+ 0 5 10 15 20 25 30 35 40 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 v a ( v ) v+ = 1.65 v , i s = 4 ma r on ? on resistance ( ) v+ = 2.3 v , i s = 8 ma v+ = 3.0 v, i s = 24 ma v+ = 4.5 v , i s = 30 ma
document number: 72648 s09-0294-rev. d, 23-feb-09 www.vishay.com 5 vishay siliconix dg3157 ac loading and waveforms notes: ? c l includes probe and jig capacitance. ? waveform 1 is for an output with internal conditions such t hat the output is low except when disabled by the output control. ? waveform 2 is for an output with internal conditions such t hat the output is high except when disabled by the output control. ? all input pulses are supplied by generators having the following characteristics: prr 10 mhz, z o = 50 . ? the outputs are measured one at a ti me with one transition per measurement. ? t plz and t phz are the same as t dis . ? t pzl and t pzh are the same as t dis . ? t plh and t phl are the same as t dis . ? v ld = 2 v+. figure 2. ac test circuit from output under test v ld r l 500 c l 50 pf load circuit r l 500 open gnd sw t plh /t phl open t plz /t pzl v ld t phz /t pzh gnd test sw figure 3. ac waveforms t r = 2.5 ns t f = 2.5 ns t f = 2.5 ns t r = 2.5 ns 3.0 v 3.0 v gnd gnd logic input switch input 10 % 10 % 10 % 10 % 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 1.5 v 90 % 90 % 90 % 90 % t w output output output t pl h t ph l v oh v ol t pz l t pl z t pz h t ph z 1.5 v v ol + 0.3 v v ol v oh v oh 0.3 v v ld 2 0 v w aveform 1 sw at v ld w aveform 2 sw at gnd propagation delay t imes enable and disable t ime-low- and high-level enabling
www.vishay.com 6 document number: 72648 s09-0294-rev. d, 23-feb-09 vishay siliconix dg3157 test circuits vishay siliconix maintains worldwide manufacturing capability. products may be manufactured at one of several qualified locatio ns. reliability data for silicon technology and package reliability represent a composite of all qualified locations. for related documents such as package/tape drawings, part marking, and reliability data, see www.vishay.com/ppg?72648 . figure 4. break-before-make interval c l (includes fixture and stra y capacitance) b 0 b 1 b 1 b 0 0 v logic input switch output v o b 0 = b 1 t r < 5 ns t f < 5 ns 90 % t d t d s a v+ gnd v + c l 35 pf v o r l 50 vv v sh v sl figure 5. charge injection off on on v s out q = out x c l c l = 1 nf r gen v out a v in = 0 ? v+ s v gen gnd v+ v+ in depends on switch configuration: input polarity determined by sense of switch. + b x v a figure 6. off-isolation s gnd 0 v, 2.4 v 10 nf a off i sol a ti on = 20 l o g v a v bx r l analyzer v+ v + com b x figure 7. channel off/on capacitance f = 1 mhz s a gnd 0 v, 2.4 v meter hp4192a impedance analyzer or equivalent 10 nf v+ v+ b x
l c e e 1 e d e 1 a 2 a a 1 1 -a- b -b- 23 654 package information vishay siliconix document number: 71154 06-jul-01 www.vishay.com 1
dim min nom max min nom max a 0.90 ? 1.10 0.035 ? 0.043 a 1 ? ? 0.10 ? ? 0.004 a 2 0.80 ? 1.00 0.031 ? 0.039 b 0.15 ? 0.30 0.006 ? 0.012 c 0.10 ? 0.25 0.004 ? 0.010 d 1.80 2.00 2.20 0.071 0.079 0.087 e 1.80 2.10 2.40 0.071 0.083 0.094 e 1 1.15 1.25 1.35 0.045 0.049 0.053 e 0.65bsc 0.026bsc e 1 1.20 1.30 1.40 0.047 0.051 0.055 l 0.10 0.20 0.30 0.004 0.008 0.012 7 nom 7 nom ecn: s-03946?rev. b, 09-jul-01 dwg: 5550
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